circuit Memory :
  module Memory :
    input clock : Clock
    input reset : UInt<1>
    output io : { imem : { flip addr : UInt<32>, inst : UInt<32>}}

    cmem mem : UInt<8> [16384] @[Memory.scala 23:16]
    node _io_imem_inst_T = add(io.imem.addr, UInt<32>("h3")) @[Memory.scala 29:22]
    node _io_imem_inst_T_1 = tail(_io_imem_inst_T, 1) @[Memory.scala 29:22]
    node _io_imem_inst_T_2 = bits(_io_imem_inst_T_1, 13, 0) @[Memory.scala 29:8]
    infer mport io_imem_inst_MPORT = mem[_io_imem_inst_T_2], clock @[Memory.scala 29:8]
    node _io_imem_inst_T_3 = add(io.imem.addr, UInt<32>("h2")) @[Memory.scala 30:22]
    node _io_imem_inst_T_4 = tail(_io_imem_inst_T_3, 1) @[Memory.scala 30:22]
    node _io_imem_inst_T_5 = bits(_io_imem_inst_T_4, 13, 0) @[Memory.scala 30:8]
    infer mport io_imem_inst_MPORT_1 = mem[_io_imem_inst_T_5], clock @[Memory.scala 30:8]
    node _io_imem_inst_T_6 = add(io.imem.addr, UInt<32>("h1")) @[Memory.scala 31:22]
    node _io_imem_inst_T_7 = tail(_io_imem_inst_T_6, 1) @[Memory.scala 31:22]
    node _io_imem_inst_T_8 = bits(_io_imem_inst_T_7, 13, 0) @[Memory.scala 31:8]
    infer mport io_imem_inst_MPORT_2 = mem[_io_imem_inst_T_8], clock @[Memory.scala 31:8]
    node _io_imem_inst_T_9 = bits(io.imem.addr, 13, 0) @[Memory.scala 32:8]
    infer mport io_imem_inst_MPORT_3 = mem[_io_imem_inst_T_9], clock @[Memory.scala 32:8]
    node io_imem_inst_lo = cat(io_imem_inst_MPORT_2, io_imem_inst_MPORT_3) @[Cat.scala 31:58]
    node io_imem_inst_hi = cat(io_imem_inst_MPORT, io_imem_inst_MPORT_1) @[Cat.scala 31:58]
    node _io_imem_inst_T_10 = cat(io_imem_inst_hi, io_imem_inst_lo) @[Cat.scala 31:58]
    io.imem.inst <= _io_imem_inst_T_10 @[Memory.scala 28:16]

